1. Field of the Invention
This invention relates generally to semiconductor manufacturing technology and, more particularly, to methods for improving the morphology of rugged polycrystalline silicon, as it relates to increased surface area of the material and its usefulness as a capacitor plate electrode in integrated circuits.
2. Description of the Prior Art
In 1965, Gordon Moore, the co-founder of Intel Corporation, observed that the number of transistors per square inch on integrated circuits had doubled every year since the invention of the integrated circuit. Moore predicted that this trend would continue for the foreseeable future. Although the pace slowed somewhat in subsequent years, the past forty years have seen a doubling of transistor density approximately every 18 months. Most experts, including Moore himself, expect this trend to continue for at least another 15 years, when the finite size of atomic particles may limit any significant increases in miniaturization.
The miniaturization trend predicted by Moore has proved applicable to nearly all types of integrated circuits, including logic circuits, microprocessors, and semiconductor memory. As the density of integrated circuits has increased, corresponding increases in device speed have been coupled with corresponding decreases in cost and power consumption per transistor.
For at least a quarter of a century, dynamic random access memory (DRAM)-despite the fact that it is generally slower than static random access memory (SRAM) of the same generation, and requires periodic refresh to prevent data volatilityxe2x80x94has established itself as the principal type of main memory for computer applications, as a result of its low cost per bit of storage. The basic units of a DRAM memory cell are a capacitor and an access transistor, through which the capacitor can be initially charged, refreshed, and xe2x80x9creadxe2x80x9d. The cell capacitor generally comprises a storage node plate that is directly coupled to the cell access transistor; a cell plate that is generally maintained at ground potential, and is common to all cells on the same chip; and a dielectric layer sandwiched between the storage node plate and the cell plate. As DRAM density increases, chip real estate available for capacitor construction must invariably decrease. However, the charge required to provide adequate functionality of memory cells and the sense amplifiers used to read their charge contents does not decrease at the same rate. Consequently, DRAM manufacturers have found it necessary to maintain cell capacitance using a variety of three-dimensional techniques, such as the construction of stacked or trench capacitors, the use of new capacitor dielectric materials having higher dielectric constants, and the use of capacitor plate material having non-smooth surfaces.
Silicon has been used extensively, both as a substrate and as a deposited material, for most past and present generations of integrated circuits. Solid silicon exists in both crystalline and amorphous forms. Crystalline silicon can be either monocrystalline or polycrystalline. The wafers, on which most integrated circuits are constructed, are typically monocrystalline (single-crystal) silicon. Under proper conditions, additional monocrystalline silicon can be epitaxially grown on a silicon wafer substrate using chemical vapor deposition. Polycrystalline silicon (often called polysilicon for short), typically results when silicon is deposited at a temperature in excess of about 580xc2x0 C. using a chemical vapor deposition process in the absence of a monocrystalline surface which could order the deposition of silicon atoms into a single-crystal matrix. At a temperature of less than about 580xc2x0 C., amorphous silicon will be deposited. The exact transition temperature, where the change from amorphous to polycrystalline silicon occurs, depends on the types of precursor compounds and certain temperature-unrelated reaction conditions used in the chemical vapor deposition process.
Polysilicon is commonly utilized as a material for both capacitor plates in DRAM memory cells, because of its compatibility with subsequent high temperature processing, thermal expansion properties compatible with those of silicon dioxide, and its ability to be conformally deposited over widely varying topography. In order for polysilicon to conduct electricity, it must be conductively doped, which can be accomplished either during the deposition process (in situ) or subsequent to its deposition via diffusion or implantation of the appropriate impurities.
It has been recognized, for about a decade, that capacitance of a capacitor formed from a polysilicon layer can be increased merely by increasing the surface roughness of the polysilicon film that is used as a capacitor storage node. As capacitance is roughly proportional to the surface area of the smallest of the two capacitor plates, capacitance can be increased if roughness of the plate contributes to its area. In order for this to occur, the dielectric layer between a DRAM cell""s storage node plate and the cell plate must be sufficiently thin to conformally coat the rough surface of the storage node. In addition, the dielectric layer must be particularly resistant to electrical breakdown, as the rough surface will suffer electrical breakdown at a much lower voltage than would a smooth surface with a dielectric layer of the same composition and thickness. By employing a relatively thin dielectric layer, the roughness on the storage node capacitor plate is transferred to the cell""s dielectric layer and, finally, to the cell plate, resulting in a larger surface area and, hence, greater capacitance than would have a similarly shaped capacitor formed from smooth polysilicon capacitive layers.
It is well known in the art that rough polysilicon, known either as rugged polysilicon or hemisherical-grain (HSG) polysilicon, can be formed by a variety of methods. The known methods include a single-step low pressure chemical vapor deposition (LPCVD), and a multi-step procedure involving depositing a layer of amorphous silicon, seeding the layer of amorphous, and annealing the seeded layer to convert the amorphous silicon to HSG. For the single-step method, silicon is deposited at a temperature between the range of temperatures where amorphous silicon is formed and the range of temperatures where polycrystalline silicon is formed. The process is typically performed within a range of about 555-568xc2x0 C. at a pressure of about 190 mtorr. Silane (SiH4) is typically used as the primary precursor for this process. For the method involving the seeding and annealing of amorphous silicon, an amorphous silicon layer is first deposited. Subsequently, the deposited layer is seeded with either silane or disilane molecules in order to form crystals upon the surface of the amorphous silicon layer. The seeded layer is then annealed in a vacuum. Amorphous silicon atoms migrate and grow grains of HSG on the silicon crystals. The anneal step can be performed at a temperature in excess of about 450xc2x0 C.
A tracing and subsequent digitization of a scanning electro micrograph of the surface of a 1.34 xcexcm square sample of a rugged polysilicon layer 100 formed using the conventional techniques heretofore described is shown in FIG. 1. It will be noted that an alternating array of plateaus 101 and valleys 102 have been formed within the rugged polysilicon layer 100, thereby increasing the surface area thereof. It will be noted that, with few exceptions, each plateau 101 appears to be interconnected with all other plateaus.
The present invention includes a method for increasing the surface area of hemispherical-grain polysilicon and for forming a storage-node capacitor plate that can be used in the manufacture of dynamic random access memories (DRAMs). The invention represents an improvement to the multi-step process described in the Background of the Invention section. As the instant process is likely to be used primarily in the manufacture of dynamic random access memories, it will be disclosed in that context. A layer of polycrystalline silicon having a thickness within a range of about 200 to 300 xc3x85 is deposited on a substrate. This layer is either in-situ doped or doped after it is deposited via implantation or diffusion. Next, an amorphous silicon layer also having a -thickness within a range of about 200 to 300 xc3x85 is deposited on top of the polycrystalline silicon layer. Hemispherical-grain (HSG) polysilicon seeds are then grown on the upper surface of the amorphous silicon layer using one of several known techniques. For example, following a dilute hydrofluoric (DHF) acid dip to remove any native oxide, the amorphous silicon is subjected to an ultra-high vacuum (UHV) condition at a temperature within a range of about 500 to 800xc2x0 C. for a period of from about 1 to 10 minutes in the presence of either silane or disilane at a concentration below about 1.0xc3x9710xe2x88x921/m3. These conditions are conducive to the growth of HSG silicon seeds on the surface of the amorphous silicon layer. An anneal sequence is then performed in the presence of silane. An initial temperature of about 550xc2x0 C. is maintained for about 3.5 minutes. At the end of that period, the temperature is ramped at a rate of 2xc2x0 C. per minutes over a period of about 8 minutes. Upon reaching a temperature of about 568xc2x0 C., that final temperature is maintained for an additional period of about 6 minutes. During the anneal sequence, silicon atoms within the amorphous silicon layer migrate to the seeded locations and incorporate themselves in the crystal matrices of the HSG seeds, thereby causing them to grow. The ramped temperature during the anneal sequence is highly effective in forming isolated grains of HSG polysilicon. The underlying doped polysilicon layer provides electrical continuity between the isolated grains of HSG polysilicon.